 # Project Setup Variables
  set PROJ_NAME "myproj"
  set PART "xc7a200tfbg676-2"
  set BOARD "xilinx.com:ac701:part0:1.3"
  #set PART "xcku040-ffva1156-2-e"
  #set BOARD "xilinx.com:kcu105:part0:1.0"
  #set PART "xc7z045ffg900-2"
  #set BOARD "xilinx.com:zc706:part0:1.1"

  # Create the project - Builds project in the current directory.
  create_project $PROJ_NAME ./$PROJ_NAME -part $PART -force
  set_property board_part $BOARD [current_project]

# Create synthesis/implementation/simulation fileset

# Create simulation only fileset

# Set individual file properties

# Set Top-level design unit

# Add ip repository path
set_property  ip_repo_paths  ./ip_repo/MiniMAC_1Ge_AXI_1.0 [current_project]
update_ip_catalog -rebuild

# Rebuild block design
source ./src/sys_ipi/design_1_bd.tcl
save_bd_design
validate_bd_design

# Add top-level block design wrapper
add_files -norecurse ./src/sys_ipi/design_1_wrapper.v

# Update compile order
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
save_bd_design

#reset_run synth_1
#reset_run impl_1

#launch_runs synth_1 -jobs 1
#wait_on_run synth_1

#launch_runs impl_1 -jobs 1
#wait_on_run impl_1

#launch_runs impl_1 -to_step write_bitstream
#wait_on_run impl_1

